Bob - I forgot to answer your question about deterministic outcome of asynchronous sample rate converter. I think that for practical purposes it is, but anytime you deal with asynchronous stuff strange things might happen. One of them is metastability. Designers fix it by making shift register that clocks signal twice to reduce chances of unknown outcome. It is a little like getting tossed coin on its edge - any flip-flop can produce delay or unknown state (in between logic levels) when clock and data change at the same time. It sound far fetched but many computer motherboards had problems because of that.