I don’t think you’re missing anything, defiantboomerang.
Shadorne, if we denote the magnitude of the maximum possible output voltage as V, I’m envisioning that one DAC chip is controlling generation of output voltages between 0 and +V, with the other DAC chip generating 0 when a positive voltage is called for, while the other DAC is controlling generation of output voltages between 0 and -V, with the first DAC generating 0 when a negative voltage is called for. The outputs of the two DACs are then combined to create the overall output of the component. The voltage generated by each DAC would of course be quantized with 20 bit resolution, which would result in 21 bit resolution over the range from +V to -V.
Best regards,
-- Al