Noshortcuts, Usarmyvet91
OK, here is how I understand it (an expert in this matter is free to correct me) - any product that uses the TI PCM27XX 'stereo DAC with USB interface' IC (the Wadia 170i uses the TI2705) inherently suffers from high(er) jitter because the PCM27XX family of ICs uses what is called adaptive clock recovery. I.E. the PCM27XX IC uses each 1mS burst of data on the USB to extract the clock from the data. The inherent flaw w/ this methodology is that
* the computer is not always punctual in comanding the iPod to send a 1ms burst of data, which means that the recovered clock freq can drift in the meantime
* there is a lot of interference in the total system & this noise can be injected into the data being recovered by the PCM27XX IC.
Thus the quality of the recovered clock signal is as good as the overall environment inside the 170i & basically, there is no fixed clock reference. The PCM27XX IC uses a 12MHz xtal oscillator (which you can see on the PCB if you open the 170i unit) but this clock is used for the clock recovery ckt. It is not used directly for the on-chip DAC. Once the clock is recovered, it is fed to an analog PLL as a reference freq & the analog PLL locks its VCO to this reference. The analog PLL VCO output is used as a clock to the on-chip DAC. PLLs are very useful in cleaning up "dirty" signals hence a lot of the phase noise of the recovered clock reference can be reduced. However, there is a limit to the amount of clean-up - the analog PLL VCO will somewhat track its noisy reference signal (depending on what the analog PLL bandwidth is). This will show up a high(er) jitter on the output digital stream.
What the modifying houses are doing is that they are improving the 12MHz clock to a Superclock (at high cost to the user). Yes, there is some benefit to making this 12MHz clock cleaner BUT it does not tackle the central issue of adaptive clock recovery using the USB data stream. Adaptive clock recovery is the central theme to the PCM27XX family operation & since it creates a jittery reference clock, the end result is jittery digital data out. So, let us say that the ROI of this mod is (very) low.
What the people, who want to sell you re-clockers, are suggesting is that you create a 2 clock system - one clock (the Wadia's) will be high(er) jitter & the 2nd clock (the re-clocker's) will be a precision clock.
In effect, let the 170i do its adaptive clock recovery thing & create a jittery digital data output stream. Then, feed this jittery digital data stream into the re-clocker running off a precision clock. The re-clocker, in all probability, has a FIFO (first-in, first-out) buffer wherein the data comes in at the jittery clock rate & gets pulled out at the precision clock rate. This is an Asynchronous Rate Conversion which converts the digital data stream from the jittery clock domain to the precision clock domain. Thus, the digital data at the re-clocker's output is very low jitter. This can now be fed into a DAC of your choice & the sonics should be much improved.
(in contrast there is no such 2 clock system native to the PCM27XX IC family so the user is stuck with the jittery recovered clock. Hence there is no method in the PCM27XX to transfer the data to a clean clock domain).
