Importance of clocking

Releasing a dirty stream to the D/A increases its processing

No it doesn’t, latency has nothing to do with it and buffers are never “underutilized” because of back signaling.

Perhaps example will help:

Worker (DAC) has to place items on conveyer belt (D/A Converter) of some machine in exactly one second spacing, but another worker (computer) hands them too slow or too fast creating uneven space between them.  Remedy for that would be shelf with many items on it (buffer).  One worker adds bunch of them (frame) to the shelf every so often and the other places items on conveyer belt in even intervals, yelling back “get more (or less) next time” to keep decent amount of them on the shelf (back signaling).

@kijanki

You are not addressing my point on processor loading. Or who else is cleaning up the mess?

@antigrunge2 What processor?  The only one that can affect timing of D/A converter is in the DAC.  It loads samples from the buffer into D/A converter at even time intervals.  It also signals back when buffer is too empty or too full. 

Sending asynchronous data in packets is reducing stress on receiving end allowing receiver to get data in the required or convenient time.

 

So where is error correction happening if not at the D/A processor?