Lynne, if you haven't already, take a look at the figures shown in the Wikipedia writeup I linked to earlier for Biphase Mark/Differential Manchester Encoding, Biphase Mark (shown in the second figure) being the encoding method used for S/PDIF. The paragraph above the figures helps to clarify them.
Think of all the waveforms shown in the figures as being graphs that depict voltage along their vertical axis, and time along their horizontal axis.
As you'll see, 1 and 0 data information is conveyed by virtue of whether one "transition" or two "transitions" occur within each "clock period" (defined below). A "transition" being defined as a CHANGE from either the higher voltage ("logic 1") state to the lower voltage ("logic 0") state, or vice versa.
The higher voltage (logic 1) state is the upper of the two possible voltage levels of each signal waveform that is shown, and the lower voltage (logic 0) state is the lower of those two levels.
A "clock period" is defined as the amount of time either between one positive-going (logic 0 to logic 1) transition of the clock waveform and the next positive-going transition of that waveform, or, equivalently, between one negative-going (logic 1 to logic 0) transition of the clock waveform and the next negative-going transition of that waveform.
That encoding method allows both clock and data to be conveyed in a single signal, as Steve and I indicated earlier.
Best,
-- Al
Think of all the waveforms shown in the figures as being graphs that depict voltage along their vertical axis, and time along their horizontal axis.
As you'll see, 1 and 0 data information is conveyed by virtue of whether one "transition" or two "transitions" occur within each "clock period" (defined below). A "transition" being defined as a CHANGE from either the higher voltage ("logic 1") state to the lower voltage ("logic 0") state, or vice versa.
The higher voltage (logic 1) state is the upper of the two possible voltage levels of each signal waveform that is shown, and the lower voltage (logic 0) state is the lower of those two levels.
A "clock period" is defined as the amount of time either between one positive-going (logic 0 to logic 1) transition of the clock waveform and the next positive-going transition of that waveform, or, equivalently, between one negative-going (logic 1 to logic 0) transition of the clock waveform and the next negative-going transition of that waveform.
That encoding method allows both clock and data to be conveyed in a single signal, as Steve and I indicated earlier.
Best,
-- Al