Steve N.
Can you please explain how the use of the pacecar reclocker would be of benefit when used between the SQBX3 and DAC1, over a good true 75 ohm tranmission line in s/pdif mode? As I understand it, the Benchmark DAC1 has an AKM 4114 S/Pdif receiver which extracts the data, and clock. This clock and data are then connected to the Analog Devices AD1896 sample rate converter. The AD1896 besides its upsample and down sample function has two clock inputs: 1 from the serial data (from the AKM), and 1 master ref clk input. The AD1896 is a fully asynchronous design, and as such the serial clock drives the data into a FIFO, while the other clock (master, a crystal in this case) controls the FIFO output port. It is this asynchronous SRC that is responsible for the isolation from the jitter-ed data. The next down stream chip is the actual DAC, an analog devices 1853. This guy also has its clock derived from a stable external reference oscillator. Thus the data and clock presented to the DAC are de-coupled from the jittery data source over the S/pdif protocol ( this is basically my understanding of Ultralock ).
It seems to me that any device inserted in the s/pdif chain as an intermediate step (between the SB3 and DAC1) is made irrelevant by this (the DAC1's) particular hardware architecture. The selected devices (particularly the SRC) in the DAC1 already offer asynchronous FIFOs.
It's not like anything done to the spdif signal can stop or change this ultralock process from happening. It IS the hardware.
I am probably missing something in my description as I have cobbled it together from existing literature and do not have the source schematics.
Can you please explain how the use of the pacecar reclocker would be of benefit when used between the SQBX3 and DAC1, over a good true 75 ohm tranmission line in s/pdif mode? As I understand it, the Benchmark DAC1 has an AKM 4114 S/Pdif receiver which extracts the data, and clock. This clock and data are then connected to the Analog Devices AD1896 sample rate converter. The AD1896 besides its upsample and down sample function has two clock inputs: 1 from the serial data (from the AKM), and 1 master ref clk input. The AD1896 is a fully asynchronous design, and as such the serial clock drives the data into a FIFO, while the other clock (master, a crystal in this case) controls the FIFO output port. It is this asynchronous SRC that is responsible for the isolation from the jitter-ed data. The next down stream chip is the actual DAC, an analog devices 1853. This guy also has its clock derived from a stable external reference oscillator. Thus the data and clock presented to the DAC are de-coupled from the jittery data source over the S/pdif protocol ( this is basically my understanding of Ultralock ).
It seems to me that any device inserted in the s/pdif chain as an intermediate step (between the SB3 and DAC1) is made irrelevant by this (the DAC1's) particular hardware architecture. The selected devices (particularly the SRC) in the DAC1 already offer asynchronous FIFOs.
It's not like anything done to the spdif signal can stop or change this ultralock process from happening. It IS the hardware.
I am probably missing something in my description as I have cobbled it together from existing literature and do not have the source schematics.