A great balanced R2R ladder DAC: Mhdt Lab Balanced Pagoda


After reviewing balanced DACs that cost right around $5000 for the Stereo Times website, I received scores of  Emails from Gon members requesting if I could find and review a truly balanced ladder R2R DAC for less then $2,500. Well, my review on the Mhdt Lab Balanced Pagoda just went up on the Stereo Times website. It will give you all the details why I put it on the " 2020 Most Wanted Component List". The Balanced Pagoda easily matched the overall performance of the twice more expensive, highly regarded DACs. The only caveat to get its best performance you most run it through the XLR analog outputs, not its single-ended RCAs, into another balanced preamplifier. Hope, you take a look at the review, if you are looking to get a balanced DAC to run in your system.
amorstereo
Hi Terry, 

I was surprised you didnt mention the AM Tubadour SE in your Pagoda review. You described it as a giant killer a year ago (you probably didnt use that term) but now I see it's the Pagoda that is in your best products list. 
I would really appreciate it if you could tell us how they compare. You write in the review the Pagoda needs to be used fully balanced to give its best. Would you say the AM is better for those of us with RCA pre/amps?

thomas
Underwood is now selling Audio GD kit; amp, dac, headphone amp, ...

Here’s snippet from their R2R dac

The R1 is an R2R full discrete DAC that uses 8 groups fully discrete R-2R DA modules to combine into a real balanced push/pull decoder. it also uses 4 group fully discrete real balanced DSD native decoders. It uses a fully discrete real balanced current transmition design. Jitter is kept ultra low by using dual ultra high frequency 90/98 MHz Accusilicon 318B femtosecond clocks to a provide synchronous clock for the whole unit without using a PLL up-frequency. The R1 works up to 32bit/384K with DSD512 asynchronous USB transfer thru the Amanero 384 FPGA synchronous clock. The entire whole digital circuit is built with single FPGA and 5 CPLD programmable chipsets to separate the different configured circuits to avoid interrupting the data stream process in parallel mode. The unit supports firmware updates future sound quality updates and all digital process mode settings are accessible by buttons on the front.