@ozzy
From the EMail , I received this morning ( it is a long text )
As you may have read, we have been working hard in development of EtherREGEN Gen2 for over 1 year—utilizing more readily available parts and incorporating a number of technical advancements. These include Gigabit capability on both the ‘A’ and ‘B’ sides of our unique active-differential-isolation moat, even lower jitter clock synthesizers, an exceptional new PHY chip, and the world’s best sine-to-square wave converter (benefiting those who chose to pair with an external 10MHz reference clock). The new version will even include a second SFP cage—on the ‘B’ side—to improve performance for users of optical endpoints.
However, every day and night we are trying to solve a last technical riddle with interfacing of two brand new special chips we have chosen. As soon as this puzzle is solved—hopefully within the next couple of weeks—we can then move on to the final round of test boards incorporating all of the elements and advancements of our new design.
Realistically, even if we solve this last programming issue next week, there time to produce next full version test board (large with lots of test points) and then actual pre-production test/beta boards all adds up to several more months before full salable production units are ready.