Thanks Steve.
I thought (from the data sheet and the DAC1 implemenation) the SRC chip keeps the two clocks separate, though: 1) The serial data side (most jitter), and 2)on board 20 something MHz crystal,the clk signal of which is fed to the SRC side, AND the DAC. Are you saying that the crystal itself is now adding to the jitter equation, or that the frequency synthesis taking place inside the SRC chip, (the source of which is the crystal) is adding the jitter?
Thanks Much
I thought (from the data sheet and the DAC1 implemenation) the SRC chip keeps the two clocks separate, though: 1) The serial data side (most jitter), and 2)on board 20 something MHz crystal,the clk signal of which is fed to the SRC side, AND the DAC. Are you saying that the crystal itself is now adding to the jitter equation, or that the frequency synthesis taking place inside the SRC chip, (the source of which is the crystal) is adding the jitter?
Thanks Much