Wow 800 psec of jitter would easily be audible. Even 20 psec jitter may be audible. This shows the importance of
1) A good modern asynchronous DAC that rejects the always present incoming jitter entirely - so you are left with inherent jitter of the DAC itself (for example Cranesong Solaris claims less than 0.5 psec jitter)
2) If you use a DAC that is not known for good incoming jitter immunity or rejection (perhaps a classic older DAC or something which just sounds good to you) then for goodness sake get Synchro-Mesh reclocker!
Be careful of asynchronous DACs that dont fully explain how they achieve a PLL. The very fact of gently adjusting the timing of a secondary clock to rapid fluctuations in the incoming clock can easily create low frequency jitter!! Some DACs have implemented a control filter on the timing adjustments that limit adjustments to less than 10Hz. Only a DAC that limits master-slave timing adjustments to BELOW the audible range (less than 10 Hz) can guarantee to eliminate all audible incoming jitter.
A poorly designed PLL may reduce jitter but create more audible jitter than a high level of random incoming jitter. The key is to understand that signal correlated jitter is much more audible than random jitter by several orders of magnitude. 20 psec jitter that is highly correlated could be much worse than 200 psec of totally random jitter. So a PLL may actually be a significant source of audible jitter!!! (sounds crazy but it is true)
1) A good modern asynchronous DAC that rejects the always present incoming jitter entirely - so you are left with inherent jitter of the DAC itself (for example Cranesong Solaris claims less than 0.5 psec jitter)
2) If you use a DAC that is not known for good incoming jitter immunity or rejection (perhaps a classic older DAC or something which just sounds good to you) then for goodness sake get Synchro-Mesh reclocker!
Be careful of asynchronous DACs that dont fully explain how they achieve a PLL. The very fact of gently adjusting the timing of a secondary clock to rapid fluctuations in the incoming clock can easily create low frequency jitter!! Some DACs have implemented a control filter on the timing adjustments that limit adjustments to less than 10Hz. Only a DAC that limits master-slave timing adjustments to BELOW the audible range (less than 10 Hz) can guarantee to eliminate all audible incoming jitter.
A poorly designed PLL may reduce jitter but create more audible jitter than a high level of random incoming jitter. The key is to understand that signal correlated jitter is much more audible than random jitter by several orders of magnitude. 20 psec jitter that is highly correlated could be much worse than 200 psec of totally random jitter. So a PLL may actually be a significant source of audible jitter!!! (sounds crazy but it is true)