Pmiguy, PLL reduces jitter but not up to the levels of async rate converter. My Benchamark DAC1 rate converter AD1896 does very fancy operation to achieve fantastic results. From the datasheet:
(full datasheet: http://www.analog.com/media/en/technical-documentation/data-sheets/AD1896.pdf)
(full datasheet: http://www.analog.com/media/en/technical-documentation/data-sheets/AD1896.pdf)
The output rate of the low-pass filter of Figure 5 would be the interpolation rate, 2^20 x 192000 kHz = 201.3 GHz. Sampling at a rate of 201.3 GHz is clearly impractical, not to mention the number of taps required to calculate each interpolated sample. However, since interpolation by 2^20 involves zero-stuffing 2^20– 1 samples between each fS_IN sample, most of the multiplies in the low-pass FIR filter are by zero. A further reduction can be realized by the fact that since only one interpolated sample is taken at the output at the fS_OUT rate, only one convolution needs to be performed per fS_OUT period instead of 2^20 convolutions. A 64-tap FIR filter for each fS_OUT sample is sufficient to suppress the images caused by the interpolation. The difficulty with the above approach is that the correct interpolated sample needs to be selected upon the arrival of fS_OUT. Since there are 2^20 possible convolutions per fS_OUT period, the arrival of the fS_OUT clock must be measured with an accuracy of 1/201.3 GHz = 4.96 ps. Measuring the fS_OUT period with a clock of 201.3 GHz frequency is clearly impossible; instead, several coarse measurements of the fS_OUT clock period are made and averaged over time.Output D/A converter operates at 110kHz only (could operate at 192kHz) to obtain lower THD distortions. I posted this technical excerpt from the data sheet only to show how complicated operation of just one small chip can be. Jitter artifacts are at very low level, but are not harmonically related (like THD) to the root frequencies thus more audible. Noise produced by the jitter is proportional to signal level and not present without it.